Photoluminescence (PL) devices find their applications in many areas such as solar cells, touch panels, UV-Blue photodetectors, as well as full-color, high quality TFT flat panel display. Such photoluminescence devices may be fabricated with nanocrystals. Traditionally, semiconductor materials such as Si, Ge are used to produce nanocrystals based on the concepts of band gap and quantum confinement effects of these materials. Exemplary PL devices are disclosed in published U.S. Patent Application 2006/0189014, which is incorporated herein in its entirety by reference for background information only. One widely-used method of fabricating silicon nanocluster is to precipitate the silicon nanocluster out of SiOx (where x<2), producing a film using chemical vapor deposition, radio frequency (RF)-sputtering, or Si implantation. This film is often called silicon-rich silicon oxide (SRSO) or silicon-rich oxide (SRO). Using the CVD or RF-sputtering processes, with a high-temperature annealing, a photoluminescence (PL) peak in the SRSO can typically be obtained in the wavelength range of 590 nanometers (nm) to 750 nm. However, these SRO materials exhibit low quantum efficiency and have a stability problem, which reduces the PL intensity height over time, and limits their application to PL devices.
Er implantation, creating Er-doped nanocrystal Si, is also used in Si-based light sources. However, state-of-the-art implantation processes have not been able to distribute the dopant uniformly, which lowers the light emitting efficiency and increases costs. At the same time, there has been no interface engineering sufficient to support the use of such a dopant. Using the Si/SiO2 superlattice structure to control crystal size results in a slow, high-temperature deposition process that cannot simultaneously control both the Si particle size and the quality Si nanocrystal/SiO2 interface. The device efficiency is very low, which limits the device applications. In order to improve the device efficiency, a large interface area must be created between nanocrystal Si and SiO2.
On the other hand, the non-volatile-memory (“NVM”) market today is dominated by floating-gate (FG) devices. According to the International Technology Roadmap for Semiconductors 2001, the tunnel oxide thickness of FG devices would remain at a level of about 9 nm for future generations. Scaling the tunnel oxide leads to anomalous charge leakage, caused by one or two defects in the oxide. Such a leakage causes the information stored in the non-volatile memory to be lost. Scaling the tunnel oxide also requires high operating voltage. Discrete charge storage bypasses this problem, hence allowing for scaling of the tunnel oxide and program/erase voltages. Reduction of the size of the charge pumps enabled by these lower voltages, as well as avoiding the double poly process required for FG devices, lowers the cost of integration especially important for embedded applications. This has triggered a renewed interest in NVM cells employing discrete, trap-like storage nodes.
Conventionally, silicon-rich nitride and silicon-rich oxide are used as the charge trapping medium to increase the retention and endurance of the information stored in the non-volatile memory devices. However, due to aforementioned manufacturing difficulties, these materials are not easily integrated in the conventional manufacturing process. A simple and efficient light-emitting device compatible with silicon, with a manufacturing process that does not require high temperature post annealing, with a process that is compatible with the conventional process to produce low temperature polysilicon thin film transistor (LTPS TFT) would be desirable in applications where photonic devices (light emitting and light detecting) are necessary.
Therefore, it is apparent that a heretofore unaddressed need exists in the art to address the aforementioned deficiencies and inadequacies.